1. Field of the Invention
The present invention relates to a power-on reset circuit for CMOS semiconductor integrated circuit.
2. Description of the Related Art
A CMOS semiconductor integrated circuit without a reset terminal includes a power-on reset circuit built therein so as to initialize an internal logic circuit or analogue circuit when the CMOS semiconductor integrated circuit is connected to a power supply.
Referring to FIG. 2, the following describes a conventional power-on reset circuit.
As a power supply voltage rises, coupling with a capacitor 111 brings the voltage of a node B close to the power supply voltage. Then, an inverter 121 turns the voltage of a node C low. The voltage of the node C is subjected to waveform shaping by a waveform shaping circuit 107, and a reset signal at a low level is output to a node D. This reset signal initializes a circuit connected to the node D. When the voltage of the node C becomes low, a NMOS transistor 103 turns OFF.
A control circuit 100 is configured to output a signal at a high level through an output terminal when an input terminal thereof is at a low level. Since a gate voltage of a NMOS transistor 102 becomes high, the NMOS transistor 102 turns ON, and electrical charge stored in the capacitor 111 is discharged through a depletion-type NMOS transistor 101. When the voltage of the node B decreases to an inversion voltage of the inverter 121, then the voltage of the node C becomes high. The voltage of the node C is subjected to waveform shaping by the waveform shaping circuit 107, and the reset signal of the node D is canceled. The voltage of the node C at a high level further turns the NMOS transistor 103 ON and causes the capacitor 111 to discharge, so that the voltage of the node B becomes the ground voltage.
Herein, the conventional power-on reset circuit is provided with a pull-down element 122 at the node C, and so has a feature that the voltage of the node C becomes less unstable even when the rising speed of the power supply voltage is slow or the power supply voltage rises from a voltage other than the ground voltage.
[Patent Document 1] Japanese Patent Application
Laid-Open No. 2009-152735